As is well known in the art, a basic RFID system includes three components: an antenna or coil; a transceiver with decoder, i.e., RFID reader or interrogator; and a transponder, i.e., RFID tag, programmed with unique information.
RFID tags are categorized as either active or passive. Active RFID tags are powered by an internal battery and are typically read/write, i.e., tag data can be rewritten and/or modified. Passive RFID tags operate without a separate external power source and obtain operating power generated from the RFID reader.
An example of a typical passive RFID tag is shown in FIG. 1. Tag 100 includes an antenna 102 that is coupled to an analog front end circuit 104, which is in communication with a digital and memory circuit 106 through receive (RX) and transmit (TX) paths. Most passive RFID tags today use some sort of electrically erasable programmable read-only memory (EEPROM) such as flash memory.
While EEPROM memory has served in passive RFID tag applications to date, the demands for greater data throughput into and out of the RFID are increasing. This can be seen for example in factory environments, and in collecting highway tolls. The EEPROM based passive RFID tags are slow and may not be suited for the higher throughput applications. Alternative, faster memories technologies such as FRAM exist that are ideally suited for these new higher speed RFID applications. However, the entire protocol associated with transferring data input and output of the RFID tag is, generally speaking, EEPROM-related. To take advantage of alternative memory technologies, such as FRAM, what is desired are extensions to the existing data protocol that is optimized for operating a passive RFID tag incorporating FRAM memory.
The EPC Global Generation 2 standard includes a published method of doing Block Writes to memory. This method is inefficient when considering the capability of faster memory technologies, such as FRAM memory.